A Makefile is only responsible for building objects in its own
directory. Files in subdirectories should be taken care of by
Makefiles in these subdirs. The build system will automatically
invoke make recursively in subdirectories, provided you let it know of
them.

To do so, obj-y and obj-m are used.
ext2 lives in a separate directory, and the Makefile present in fs/
tells kbuild to descend down using the following assignment.

Example:
        #fs/Makefile
        obj-$(CONFIG_EXT2_FS) += ext2/

If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
the corresponding obj- variable will be set, and kbuild will descend
down in the ext2 directory.
Kbuild only uses this information to decide that it needs to visit
the directory, it is the Makefile in the subdirectory that
specifies what is modules and what is built-in.

It is good practice to use a CONFIG_ variable when assigning directory
names. This allows kbuild to totally skip the directory if the
corresponding CONFIG_ option is neither 'y' nor 'm'.

EXTRA_CFLAGS, EXTRA_AFLAGS, EXTRA_LDFLAGS, EXTRA_ARFLAGS

All the EXTRA_ variables apply only to the kbuild makefile
where they are assigned. The EXTRA_ variables apply to all
commands executed in the kbuild makefile.

$(EXTRA_CFLAGS) specifies options for compiling C files with
$(CC).

Example:
        # drivers/sound/emu10k1/Makefile
        EXTRA_CFLAGS += -I$(obj)
        ifdef DEBUG
            EXTRA_CFLAGS += -DEMU10K1_DEBUG
        endif

This variable is necessary because the top Makefile owns the
variable $(CFLAGS) and uses it for compilation flags for the
entire tree.

$(EXTRA_AFLAGS) is a similar string for per-directory options
when compiling assembly language source.

Example:
        #arch/x86_64/kernel/Makefile
        EXTRA_AFLAGS := -traditional

$(EXTRA_LDFLAGS) and $(EXTRA_ARFLAGS) are similar strings for
per-directory options to $(LD) and $(AR).

Example:
        #arch/m68k/fpsp040/Makefile
        EXTRA_LDFLAGS := -x

CFLAGS_$@, AFLAGS_$@

CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
kbuild makefile.

$(CFLAGS_$@) specifies per-file options for $(CC).  The $@
part has a literal value which specifies the file that it is for.

Example:
        # drivers/scsi/Makefile
        CFLAGS_aha152x.o =   -DAHA152X_STAT -DAUTOCONF
        CFLAGS_gdth.o    = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ /
                             -DGDTH_STATISTICS
        CFLAGS_seagate.o =   -DARBITRATE -DPARITY -DSEAGATE_USE_ASM

These three lines specify compilation flags for aha152x.o,
gdth.o, and seagate.o

$(AFLAGS_$@) is a similar feature for source files in assembly
languages.

Example:
        # arch/arm/kernel/Makefile
        AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
        AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional

Kbuild tracks dependencies on the following:
1) All prerequisite files (both *.c and *.h)
2) CONFIG_ options used in all prerequisite files
3) Command-line used to compile target

Thus, if you change an option to $(CC) all affected files will
be re-compiled.

Special rules are used when the kbuild infrastructure does
not provide the required support. A typical example is
header files generated during the build process.
Another example are the architecture-specific Makefiles which
need special rules to prepare boot images etc.

Special rules are written as normal Make rules.
Kbuild is not executing in the directory where the Makefile is
located, so all special rules shall provide a relative
path to prerequisite files and target files.

Two variables are used when defining special rules:

$(src)
    $(src) is a relative path which points to the directory
    where the Makefile is located. Always use $(src) when
    referring to files located in the src tree.

$(obj)
    $(obj) is a relative path which points to the directory
    where the target is saved. Always use $(obj) when
    referring to generated files.

Example:
        #drivers/scsi/Makefile
        $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
                $(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl

This is a special rule, following the normal syntax
required by make.
The target file depends on two prerequisite files. References
to the target file are prefixed with $(obj), references
to prerequisites are referenced with $(src) (because they are not
generated files).

The kernel may be built with several different versions of
$(CC), each supporting a unique set of features and options.
kbuild provide basic support to check for valid options for $(CC).
$(CC) is usually the gcc compiler, but other alternatives are
available.

as-option
    as-option is used to check if $(CC) -- when used to compile
    assembler (*.S) files -- supports the given option. An optional
    second option may be specified if the first option is not supported.

Example:
        #arch/sh/Makefile
        cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)

In the above example, cflags-y will be assigned the option
-Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
The second argument is optional, and if supplied will be used
if first argument is not supported.

ld-option
    ld-option is used to check if $(CC) when used to link object files
    supports the given option.  An optional second option may be
    specified if first option are not supported.

Example:
        #arch/i386/kernel/Makefile
        vsyscall-flags += $(call ld-option, -Wl$(comma)--hash-style=sysv)

In the above example, vsyscall-flags will be assigned the option
-Wl$(comma)--hash-style=sysv if it is supported by $(CC).
The second argument is optional, and if supplied will be used
if first argument is not supported.

as-instr
    as-instr checks if the assembler reports a specific instruction
    and then outputs either option1 or option2
    C escapes are supported in the test instruction

cc-option
    cc-option is used to check if $(CC) supports a given option, and not
    supported to use an optional second option.

Example:
        #arch/i386/Makefile
        cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)

In the above example, cflags-y will be assigned the option
-march=pentium-mmx if supported by $(CC), otherwise -march=i586.
The second argument to cc-option is optional, and if omitted,
cflags-y will be assigned no value if first option is not supported.

cc-option-yn
     cc-option-yn is used to check if gcc supports a given option
     and return 'y' if supported, otherwise 'n'.

Example:
        #arch/ppc/Makefile
        biarch := $(call cc-option-yn, -m32)
        aflags-$(biarch) += -a32
        cflags-$(biarch) += -m32

In the above example, $(biarch) is set to y if $(CC) supports the -m32
option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
and $(cflags-y) will be assigned the values -a32 and -m32,
respectively.

cc-option-align
    gcc versions >= 3.0 changed the type of options used to specify
    alignment of functions, loops etc. $(cc-option-align), when used
    as prefix to the align options, will select the right prefix:
    gcc < 3.00
            cc-option-align = -malign
    gcc >= 3.00
            cc-option-align = -falign

Example:
        CFLAGS += $(cc-option-align)-functions=4

In the above example, the option -falign-functions=4 is used for
gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.

cc-version
    cc-version returns a numerical version of the $(CC) compiler version.
    The format is <major><minor> where both are two digits. So for example
    gcc 3.41 would return 0341.
    cc-version is useful when a specific $(CC) version is faulty in one
    area, for example -mregparm=3 was broken in some gcc versions
    even though the option was accepted by gcc.

Example:
        #arch/i386/Makefile
        cflags-y += $(shell /
        if [ $(call cc-version) -ge 0300 ] ; then /
                echo "-mregparm=3"; fi ;)

In the above example, -mregparm=3 is only used for gcc version greater
than or equal to gcc 3.0.

cc-ifversion
    cc-ifversion tests the version of $(CC) and equals last argument if
    version expression is true.

Example:
        #fs/reiserfs/Makefile
        EXTRA_CFLAGS := $(call cc-ifversion, -lt, 0402, -O1)

In this example, EXTRA_CFLAGS will be assigned the value -O1 if the
$(CC) version is less than 4.2.
cc-ifversion takes all the shell operators:
-eq, -ne, -lt, -le, -gt, and -ge
The third parameter may be a text as in this example, but it may also
be an expanded variable or a macro.

cc-fullversion
    cc-fullversion is useful when the exact version of gcc is needed.
    One typical use-case is when a specific GCC version is broken.
    cc-fullversion points out a more specific version than cc-version does.

Example:
        #arch/powerpc/Makefile
        $(Q)if test "$(call cc-fullversion)" = "040200" ; then /
                echo -n '*** GCC-4.2.0 cannot compile the 64-bit powerpc ' ; /
                false ; /
        fi

In this example for a specific GCC version the build will error out explaining
to the user why it stops.

In some cases there is a need to compile and run a program on the
computer where the build is running.
The following line tells kbuild that the program bin2hex shall be
built on the build host.

Example:
        hostprogs-y := bin2hex

Kbuild assumes in the above example that bin2hex is made from a single
c-source file named bin2hex.c located in the same directory as
the Makefile.

Host programs can be made up based on composite objects.
The syntax used to define composite objects for host programs is
similar to the syntax used for kernel objects.
$(<executable>-objs) lists all objects used to link the final
executable.

Example:
        #scripts/lxdialog/Makefile
        hostprogs-y   := lxdialog
        lxdialog-objs := checklist.o lxdialog.o

Objects with extension .o are compiled from the corresponding .c
files. In the above example, checklist.c is compiled to checklist.o
and lxdialog.c is compiled to lxdialog.o.
Finally, the two .o files are linked to the executable, lxdialog.
Note: The syntax <executable>-y is not permitted for host-programs.

Objects with extension .so are considered shared libraries, and
will be compiled as position independent objects.
Kbuild provides support for shared libraries, but the usage
shall be restricted.
In the following example the libkconfig.so shared library is used
to link the executable conf.

Example:
        #scripts/kconfig/Makefile
        hostprogs-y     := conf
        conf-objs       := conf.o libkconfig.so
        libkconfig-objs := expr.o type.o

Shared libraries always require a corresponding -objs line, and
in the example above the shared library libkconfig is composed by
the two objects expr.o and type.o.
expr.o and type.o will be built as position independent code and
linked as a shared library libkconfig.so. C++ is not supported for
shared libraries.

kbuild offers support for host programs written in C++. This was
introduced solely to support kconfig, and is not recommended
for general use.

Example:
        #scripts/kconfig/Makefile
        hostprogs-y   := qconf
        qconf-cxxobjs := qconf.o

In the example above the executable is composed of the C++ file
qconf.cc - identified by $(qconf-cxxobjs).

If qconf is composed by a mixture of .c and .cc files, then an
additional line can be used to identify this.

Example:
        #scripts/kconfig/Makefile
        hostprogs-y   := qconf
        qconf-cxxobjs := qconf.o
        qconf-objs    := check.o

When compiling host programs, it is possible to set specific flags.
The programs will always be compiled utilising $(HOSTCC) passed
the options specified in $(HOSTCFLAGS).
To set flags that will take effect for all host programs created
in that Makefile, use the variable HOST_EXTRACFLAGS.

Example:
        #scripts/lxdialog/Makefile
        HOST_EXTRACFLAGS += -I/usr/include/ncurses

To set specific flags for a single file the following construction
is used:

Example:
        #arch/ppc64/boot/Makefile
        HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)

It is also possible to specify additional options to the linker.

Example:
        #scripts/kconfig/Makefile
        HOSTLOADLIBES_qconf := -L$(QTDIR)/lib

When linking qconf, it will be passed the extra option
"-L$(QTDIR)/lib".

Kbuild will only build host-programs when they are referenced
as a prerequisite.
This is possible in two ways:

(1) List the prerequisite explicitly in a special rule.

Example:
        #drivers/pci/Makefile
        hostprogs-y := gen-devlist
        $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
                ( cd $(obj); ./gen-devlist ) < $<

The target $(obj)/devlist.h will not be built before
$(obj)/gen-devlist is updated. Note that references to
the host programs in special rules must be prefixed with $(obj).

(2) Use $(always)
When there is no suitable special rule, and the host program
shall be built when a makefile is entered, the $(always)
variable shall be used.

Example:
        #scripts/lxdialog/Makefile
        hostprogs-y   := lxdialog
        always        := $(hostprogs-y)

This will tell kbuild to build lxdialog even if not referenced in
any rule.

A typical pattern in a Kbuild file looks like this:

Example:
        #scripts/Makefile
        hostprogs-$(CONFIG_KALLSYMS) += kallsyms

Kbuild knows about both 'y' for built-in and 'm' for module.
So if a config symbol evaluate to 'm', kbuild will still build
the binary. In other words, Kbuild handles hostprogs-m exactly
like hostprogs-y. But only hostprogs-y is recommended to be used
when no CONFIG symbols are involved.

Example:
        #drivers/pci/Makefile
        clean-files := devlist.h classlist.h

Example:
        #scripts/package/Makefile
        clean-dirs := $(objtree)/debian/

Example:
        #arch/i386/boot/Makefile
        subdir- := compressed/

Example:
        #arch/i386/Makefile
        archclean:
                $(Q)$(MAKE) $(clean)=arch/i386/boot

LDFLAGS             Generic $(LD) options

Flags used for all invocations of the linker.
Often specifying the emulation is sufficient.

Example:
        #arch/s390/Makefile
        LDFLAGS         := -m elf_s390
Note: EXTRA_LDFLAGS and LDFLAGS_$@ can be used to further customise
the flags used. See chapter 7.

LDFLAGS_MODULE      Options for $(LD) when linking modules

LDFLAGS_MODULE is used to set specific flags for $(LD) when
linking the .ko files used for modules.
Default is "-r", for relocatable output.

LDFLAGS_vmlinux     Options for $(LD) when linking vmlinux

LDFLAGS_vmlinux is used to specify additional flags to pass to
the linker when linking the final vmlinux image.
LDFLAGS_vmlinux uses the LDFLAGS_$@ support.

Example:
        #arch/i386/Makefile
        LDFLAGS_vmlinux := -e stext

OBJCOPYFLAGS        objcopy flags

When $(call if_changed,objcopy) is used to translate a .o file,
the flags specified in OBJCOPYFLAGS will be used.
$(call if_changed,objcopy) is often used to generate raw binaries on
vmlinux.

Example:
        #arch/s390/Makefile
        OBJCOPYFLAGS := -O binary

#arch/s390/boot/Makefile
$(obj)/image: vmlinux FORCE
        $(call if_changed,objcopy)

In this example, the binary $(obj)/image is a binary version of
vmlinux. The usage of $(call if_changed,xxx) will be described later.

AFLAGS              $(AS) assembler flags

Default value - see top level Makefile
Append or modify as required per architecture.

Example:
        #arch/sparc64/Makefile
        AFLAGS += -m64 -mcpu=ultrasparc

CFLAGS              $(CC) compiler flags

Default value - see top level Makefile
Append or modify as required per architecture.

Often, the CFLAGS variable depends on the configuration.

Example:
        #arch/i386/Makefile
        cflags-$(CONFIG_M386) += -march=i386
        CFLAGS += $(cflags-y)

Many arch Makefiles dynamically run the target C compiler to
probe supported options:

#arch/i386/Makefile

...
cflags-$(CONFIG_MPENTIUMII)     += $(call cc-option,/
                                -march=pentium2,-march=i686)
...
# Disable unit-at-a-time mode ...
CFLAGS += $(call cc-option,-fno-unit-at-a-time)
...

The first example utilises the trick that a config option expands
to 'y' when selected.

CFLAGS_KERNEL       $(CC) options specific for built-in

$(CFLAGS_KERNEL) contains extra C compiler flags used to compile
resident kernel code.

CFLAGS_MODULE       $(CC) options specific for modules

$(CFLAGS_MODULE) contains extra C compiler flags used to compile code
for loadable kernel modules.

The archprepare: rule is used to list prerequisites that need to be
built before starting to descend down in the subdirectories.
This is usually used for header files containing assembler constants.

Example:
#arch/arm/Makefile
archprepare: maketools

In this example, the file target maketools will be processed
before descending down in the subdirectories.
See also chapter XXX-TODO that describe how kbuild supports
generating offset header files.

An arch Makefile cooperates with the top Makefile to define variables
which specify how to build the vmlinux file.  Note that there is no
corresponding arch-specific section for modules; the module-building
machinery is all architecture-independent.

head-y, init-y, core-y, libs-y, drivers-y, net-y

$(head-y) lists objects to be linked first in vmlinux.
$(libs-y) lists directories where a lib.a archive can be located.
The rest list directories where a built-in.o object file can be
located.

$(init-y) objects will be located after $(head-y).
Then the rest follows in this order:
$(core-y), $(libs-y), $(drivers-y) and $(net-y).

The top level Makefile defines values for all generic directories,
and arch/$(ARCH)/Makefile only adds architecture-specific directories.

Example:
        #arch/sparc64/Makefile
        core-y += arch/sparc64/kernel/
        libs-y += arch/sparc64/prom/ arch/sparc64/lib/
        drivers-$(CONFIG_OPROFILE)  += arch/sparc64/oprofile/

An arch Makefile specifies goals that take the vmlinux file, compress
it, wrap it in bootstrapping code, and copy the resulting files
somewhere. This includes various kinds of installation commands.
The actual goals are not standardized across architectures.

It is common to locate any additional processing in a boot/
directory below arch/$(ARCH)/.

Kbuild does not provide any smart way to support building a
target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
call make manually to build a target in boot/.

The recommended approach is to include shortcuts in
arch/$(ARCH)/Makefile, and use the full path when calling down
into the arch/$(ARCH)/boot/Makefile.

Example:
        #arch/i386/Makefile
        boot := arch/i386/boot
        bzImage: vmlinux
                $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@

"$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
make in a subdirectory.

There are no rules for naming architecture-specific targets,
but executing "make help" will list all relevant targets.
To support this, $(archhelp) must be defined.

Example:
        #arch/i386/Makefile
        define archhelp
          echo  '* bzImage      - Image (arch/$(ARCH)/boot/bzImage)'
        endif

When make is executed without arguments, the first goal encountered
will be built. In the top level Makefile the first goal present
is all:.
An architecture shall always, per default, build a bootable image.
In "make help", the default goal is highlighted with a '*'.
Add a new prerequisite to all: to select a default goal different
from vmlinux.

Example:
        #arch/i386/Makefile
        all: bzImage

When "make" is executed without arguments, bzImage will be built.

extra-y

extra-y specify additional targets created in the current
directory, in addition to any targets specified by obj-*.

Listing all targets in extra-y is required for two purposes:
1) Enable kbuild to check changes in command lines
   - When $(call if_changed,xxx) is used
2) kbuild knows what files to delete during "make clean"

Example:
        #arch/i386/kernel/Makefile
        extra-y := head.o init_task.o

In this example, extra-y is used to list object files that
shall be built, but shall not be linked as part of built-in.o.

Kbuild provides a few macros that are useful when building a
boot image.

if_changed

if_changed is the infrastructure used for the following commands.

Usage:
        target: source(s) FORCE
                $(call if_changed,ld/objcopy/gzip)

When the rule is evaluated, it is checked to see if any files
need an update, or the command line has changed since the last
invocation. The latter will force a rebuild if any options
to the executable have changed.
Any target that utilises if_changed must be listed in $(targets),
otherwise the command line check will fail, and the target will
always be built.
Assignments to $(targets) are without $(obj)/ prefix.
if_changed may be used in conjunction with custom commands as
defined in 6.7 "Custom kbuild commands".

Note: It is a typical mistake to forget the FORCE prerequisite.
Another common pitfall is that whitespace is sometimes
significant; for instance, the below will fail (note the extra space
after the comma):
        target: source(s) FORCE
#WRONG!#        $(call if_changed, ld/objcopy/gzip)

ld
    Link target. Often, LDFLAGS_$@ is used to set specific options to ld.

objcopy
    Copy binary. Uses OBJCOPYFLAGS usually specified in
    arch/$(ARCH)/Makefile.
    OBJCOPYFLAGS_$@ may be used to set additional options.

gzip
    Compress target. Use maximum compression to compress target.

Example:
        #arch/i386/boot/Makefile
        LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
        LDFLAGS_setup    := -Ttext 0x0 -s --oformat binary -e begtext

targets += setup setup.o bootsect bootsect.o
$(obj)/setup $(obj)/bootsect: %: %.o FORCE
        $(call if_changed,ld)

In this example, there are two possible targets, requiring different
options to the linker. The linker options are specified using the
LDFLAGS_$@ syntax - one for each potential target.
$(targets) are assigned all potential targets, by which kbuild knows
the targets and will:
        1) check for commandline changes
        2) delete target during make clean

The ": %: %.o" part of the prerequisite is a shorthand that
free us from listing the setup.o and bootsect.o files.
Note: It is a common mistake to forget the "target :=" assignment,
      resulting in the target file being recompiled for no
      obvious reason.

When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
of a command is normally displayed.
To enable this behaviour for custom commands kbuild requires
two variables to be set:
quiet_cmd_<command>     - what shall be echoed
      cmd_<command>     - the command to execute

Example:
        #
        quiet_cmd_image = BUILD   $@
              cmd_image = $(obj)/tools/build $(BUILDFLAGS) /
                                             $(obj)/vmlinux.bin > $@

targets += bzImage
$(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
        $(call if_changed,image)
        @echo 'Kernel: $@ is ready'

When updating the $(obj)/bzImage target, the line

BUILD    arch/i386/boot/bzImage

will be displayed with "make KBUILD_VERBOSE=0".

When the vmlinux image is built, the linker script
arch/$(ARCH)/kernel/vmlinux.lds is used.
The script is a preprocessed variant of the file vmlinux.lds.S
located in the same directory.
kbuild knows .lds files and includes a rule *lds.S -> *lds.

Example:
        #arch/i386/kernel/Makefile
        always := vmlinux.lds

#Makefile
export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)

The assignment to $(always) is used to tell kbuild to build the
target vmlinux.lds.
The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
specified options when building the target vmlinux.lds.

When building the *.lds target, kbuild uses the variables:
CPPFLAGS        : Set in top-level Makefile
EXTRA_CPPFLAGS  : May be set in the kbuild makefile
CPPFLAGS_$(@F)  : Target specific flags.
                  Note that the full filename is used in this
                  assignment.

The kbuild infrastructure for *lds file are used in several
architecture-specific files.

VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION

These variables define the current kernel version.  A few arch
Makefiles actually use these values directly; they should use
$(KERNELRELEASE) instead.

$(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
three-part version number, such as "2", "4", and "0".  These three
values are always numeric.

$(EXTRAVERSION) defines an even tinier sublevel for pre-patches
or additional patches.  It is usually some non-numeric string
such as "-pre4", and is often blank.

KERNELRELEASE

$(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
for constructing installation directory names or showing in
version strings.  Some arch Makefiles use it for this purpose.

ARCH

This variable defines the target architecture, such as "i386",
"arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
determine which files to compile.

By default, the top Makefile sets $(ARCH) to be the same as the
host system architecture.  For a cross build, a user may
override the value of $(ARCH) on the command line:

make ARCH=m68k ...

INSTALL_PATH

This variable defines a place for the arch Makefiles to install
the resident kernel image and System.map file.
Use this for architecture-specific install targets.

INSTALL_MOD_PATH, MODLIB

$(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
installation.  This variable is not defined in the Makefile but
may be passed in by the user if desired.

$(MODLIB) specifies the directory for module installation.
The top Makefile defines $(MODLIB) to
$(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE).  The user may
override this value on the command line if desired.

INSTALL_MOD_STRIP

If this variable is specified, will cause modules to be stripped
after they are installed.  If INSTALL_MOD_STRIP is '1', then the
default option --strip-debug will be used.  Otherwise,
INSTALL_MOD_STRIP will used as the option(s) to the strip command.