ESP32S3获取系统各时钟
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ESP32S3获取系统各时钟
例程说明
- Python版本: Python 3.12.3
- ninja版本 : ninja version 1.11.1
- CMake版本 : cmake version 3.28.3
- 芯片型号 : ESP32-S3
- IDF版本 : ESP-IDF v5.4.1-dirty
一、获取系统时钟
#include "sys_clock.h"
#include "esp_private/esp_clk.h"
#include "esp_chip_info.h"
#include "esp_clk_tree.h"
#include "soc/rtc.h"
#include "nvs_flash.h"
#include "esp_system.h"
#include "esp_psram.h"
#include "esp_flash.h"
void system_clock_info(void)
{
uint32_t flash_size = 0;
uint32_t cpu, rtc_fast, rtc_slow, apb;
uint32_t pll_80m, pll_160m, pll_d2;
uint32_t xtal32k, rc_fast, rc_fast_d256, xtal, temp_sensor;
esp_flash_get_size(NULL, &flash_size);
printf("CPU FRQ :%dHZ\r\n", esp_clk_cpu_freq());
printf("APB FRQ :%dHZ\r\n", esp_clk_apb_freq());
printf("XTAL FRQ :%dHZ\r\n", esp_clk_xtal_freq());
printf("RTC Slow FRQ:%ldHZ\r\n", rtc_clk_slow_freq_get_hz());
printf("FLASH Size :%ldMB\r\n",flash_size / (1024 * 1024));
printf("PSRAM Size :%dMB\r\n", esp_psram_get_size() / (1024 * 1024));
printf("\r\n");
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_CPU, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &cpu);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_RTC_FAST, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &rtc_fast);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_RTC_SLOW, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &rtc_slow);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_APB, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &apb);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_PLL_F80M, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &pll_80m);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_PLL_F160M, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &pll_160m);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_PLL_D2, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &pll_d2);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_XTAL32K, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &xtal32k);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_RC_FAST, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &rc_fast);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_RC_FAST_D256, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &rc_fast_d256);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &xtal);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_TEMP_SENSOR, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &temp_sensor);
printf("RC FAST D256 CLK:%ldHZ\r\n", rc_fast_d256);
printf("TEMP SENSOR CLK :%ldHZ\r\n", temp_sensor);
printf("PLL 160M CLK :%ldHZ\r\n", pll_160m);
printf("RTC FAST CLK :%ldHZ\r\n", rtc_fast);
printf("RTC SLOW CLK :%ldHZ\r\n", rtc_slow);
printf("XTAL 32K CLK :%ldHZ\r\n", xtal32k);
printf("PLL 80M CLK :%ldHZ\r\n", pll_80m);
printf("RC FAST CLK :%ldHZ\r\n", rc_fast);
printf("PLL D2 CLK :%ldHZ\r\n", pll_d2);
printf("XTAL CLK :%ldHZ\r\n", xtal);
printf("APB CLK :%ldHZ\r\n", apb);
printf("CPU CLK :%ldHZ\r\n", cpu);
}
二、主函数
#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "nvs_flash.h"
#include "esp_system.h"
#include "esp_chip_info.h"
#include "esp_psram.h"
#include "esp_flash.h"
#include "driver/gpio.h"
#include "sys_clock.h"
void app_main(void)
{
esp_err_t ret;
uint32_t flash_size;
esp_chip_info_t chip_info;
ret = nvs_flash_init();
if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND)
{
ESP_ERROR_CHECK(nvs_flash_erase());
ret = nvs_flash_init();
}
esp_flash_get_size(NULL, &flash_size);
esp_chip_info(&chip_info);
printf("内核CPU数量%d\n",chip_info.cores);
printf("FLASH size:%ld MB flash\r\n",flash_size / (1024 * 1024));
printf("PSRAM size:%d bytes\r\n", esp_psram_get_size());
while(1)
{
system_clock_info();
vTaskDelay(5000);
}
}

三、CMakeLists文件
# CMake最低版本
cmake_minimum_required(VERSION 3.16)
# 指定额外组件搜索目录
set(EXTRA_COMPONENT_DIRS components/Middlewares)
# 强制编译器彩色显示编译信息
add_compile_options(-fdiagnostics-color=always)
# 指定编译目标芯片
set(IDF_TARGET esp32s3)
# 日志输出命令
message(STATUS "Current IDF_PATH from environment: $ENV{IDF_PATH}")
# ESP-IDF核心构建脚本启动ESP-IDF构建系统
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
# 定义工程名称
project(main)
idf_component_register(SRCS "main.c"
INCLUDE_DIRS ".")
set(src_dirs
Clock)
set(include_dirs
Clock)
set(requires driver
nvs_flash
esp_psram
spi_flash)
idf_component_register(SRC_DIRS ${src_dirs}
INCLUDE_DIRS ${include_dirs}
REQUIRES ${requires})
component_compile_options(-ffast-math -O3 -Wno-error=format -Wno-format)
四、运行结果
I (27) boot: ESP-IDF v5.4.1-dirty 2nd stage bootloader
I (27) boot: compile time Feb 4 2026 16:52:58
I (27) boot: Multicore bootloader
I (28) boot: chip revision: v0.2
I (30) boot: efuse block revision: v1.3
I (34) qio_mode: Enabling default flash chip QIO
I (38) boot.esp32s3: Boot SPI Speed : 80MHz
I (42) boot.esp32s3: SPI Mode : QIO
I (46) boot.esp32s3: SPI Flash Size : 16MB
I (50) boot: Enabling RNG early entropy source...
I (54) boot: Partition Table:
I (57) boot: ## Label Usage Type ST Offset Length
I (63) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (70) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (76) boot: 2 factory factory app 00 00 00010000 001f0000
I (83) boot: 3 vfs Unknown data 01 81 00200000 00a00000
I (89) boot: 4 storage Unknown data 01 82 00c00000 00400000
I (96) boot: End of partition table
I (99) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=0ab28h ( 43816) map
I (113) esp_image: segment 1: paddr=0001ab50 vaddr=3fc93e00 size=02ef4h ( 12020) load
I (116) esp_image: segment 2: paddr=0001da4c vaddr=40374000 size=025cch ( 9676) load
I (123) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=1ac44h (109636) map
I (145) esp_image: segment 4: paddr=0003ac6c vaddr=403765cc size=0d7a0h ( 55200) load
I (156) esp_image: segment 5: paddr=00048414 vaddr=600fe100 size=0001ch ( 28) load
I (162) boot: Loaded app from partition at offset 0x10000
I (163) boot: Disabling RNG early entropy source...
I (174) octal_psram: vendor id : 0x0d (AP)
I (174) octal_psram: dev id : 0x02 (generation 3)
I (174) octal_psram: density : 0x03 (64 Mbit)
I (176) octal_psram: good-die : 0x01 (Pass)
I (180) octal_psram: Latency : 0x01 (Fixed)
I (185) octal_psram: VCC : 0x01 (3V)
I (189) octal_psram: SRF : 0x01 (Fast Refresh)
I (194) octal_psram: BurstType : 0x01 (Hybrid Wrap)
I (199) octal_psram: BurstLen : 0x01 (32 Byte)
I (203) octal_psram: Readlatency : 0x02 (10 cycles@Fixed)
I (208) octal_psram: DriveStrength: 0x00 (1/1)
I (213) MSPI Timing: PSRAM timing tuning index: 5
I (217) esp_psram: Found 8MB PSRAM device
I (221) esp_psram: Speed: 80MHz
I (224) cpu_start: Multicore app
I (659) esp_psram: SPI SRAM memory test OK
I (668) cpu_start: Pro cpu start user code
I (668) cpu_start: cpu freq: 240000000 Hz
I (668) app_init: Application information:
I (668) app_init: Project name: main
I (672) app_init: App version: 1
I (675) app_init: Compile time: Feb 4 2026 16:52:39
I (680) app_init: ELF file SHA256: b10cd56c6...
I (684) app_init: ESP-IDF: v5.4.1-dirty
I (689) efuse_init: Min chip rev: v0.0
I (692) efuse_init: Max chip rev: v0.99
I (696) efuse_init: Chip rev: v0.2
I (700) heap_init: Initializing. RAM available for dynamic allocation:
I (707) heap_init: At 3FC97658 len 000520B8 (328 KiB): RAM
I (712) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
I (717) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (722) heap_init: At 600FE11C len 00001ECC (7 KiB): RTCRAM
I (727) esp_psram: Adding pool of 8192K of PSRAM memory to heap allocator
I (734) spi_flash: detected chip: generic
I (738) spi_flash: flash io: qio
I (741) sleep_gpio: Configure to isolate all GPIO pins in sleep state
I (747) sleep_gpio: Enable automatic switching of GPIO sleep configuration
I (754) main_task: Started on CPU0
I (778) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations
I (778) main_task: Calling app_main()
内核CPU数量2
FLASH size:16 MB flash
PSRAM size:8388608 bytes
CPU FRQ :240000000HZ
APB FRQ :80000000HZ
XTAL FRQ:40000000HZ
RTC Slow FRQ:136000HZ
FLASH Size :16MB
PSRAM Size :8MB
RC FAST D256 CLK:68359HZ
TEMP SENSOR CLK :17500000HZ
PLL 160M CLK :160000000HZ
RTC FAST CLK :17500000HZ
RTC SLOW CLK :136000HZ
XTAL 32K CLK :32768HZ
PLL 80M CLK :80000000HZ
RC FAST CLK :17500000HZ
PLL D2 CLK :240000000HZ
XTAL CLK :40000000HZ
APB CLK :80000000HZ
CPU CLK :240000000HZ

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