COPIED FROM:

http://fibrevillage.com/sysadmin/243-edac-error-detection-and-correction

https://01.org/linuxgraphics/gfx-docs/drm/driver-api/edac.html

 

 

1. Error Detection And Correction (EDAC) Devices

Main Concepts used at the EDAC subsystem

There are several things to be aware of that aren't at all obvious, like sockets, *socket sets, banks, rows, chip-select rows, channels, etc...

These are some of the many terms that are thrown about that don't always mean what people think they mean (Inconceivable!). In the interest of creating a common ground for discussion, terms and their definitions will be established.

• Memory devices

The individual DRAM chips on a memory stick. These devices commonly output 4 and 8 bits each (x4, x8). Grouping several of these in parallel provides the number of bits that the memory controller expects: typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.

• Memory Stick

A printed circuit board that aggregates multiple memory devices in parallel. In general, this is the Field Replaceable Unit (FRU) which gets replaced, in the case of excessive errors. Most often it is also called DIMM (Dual Inline Memory Module).

• Memory Socket

A physical connector on the motherboard that accepts a single memory stick. Also called as "slot" on several datasheets.

• Channel

A memory controller channel, responsible to communicate with a group of DIMMs. Each channel has its own independent control (command) and data bus, and can be used independently or grouped with other channels.

• Branch

It is typically the highest hierarchy on a Fully-Buffered DIMM memory controller. Typically, it contains two channels. Two channels at the same branch can be used in single mode or in lockstep mode. When lockstep is enabled, the cacheline is doubled, but it generally brings some performance penalty. Also, it is generally not possible to point to just one memory stick when an error occurs, as the error correction code is calculated using two DIMMs instead of one. Due to that, it is capable of correcting more errors than on single mode.

• Single-channel

The data accessed by the memory controller is contained into one dimm only. E. g. if the data is 64 bits-wide, the data flows to the CPU using one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3 memories. FB-DIMM and RAMBUS use a different concept for channel, so this concept doesn't apply there.

• Double-channel

The data size accessed by the memory controller is interlaced into two dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72 bits with ECC), the data flows to the CPU using a 128 bits parallel access.

• Chip-select row

This is the name of the DRAM signal used to select the DRAM ranks to be accessed. Common chip-select rows for single channel are 64 bits, for dual channel 128 bits. It may not be visible by the memory controller, as some DIMM types have a memory buffer that can hide direct access to it from the Memory Controller.

• Single-Ranked stick

A Single-ranked stick has 1 chip-select row of memory. Motherboards commonly drive two chip-select pins to a memory stick. A single-ranked stick, will occupy only one of those rows. The other will be unused.

• Double-Ranked stick

A double-ranked stick has two chip-select rows which access different sets of memory devices. The two rows cannot be accessed concurrently.

• Double-sided stick

DEPRECATED TERM, see Double-Ranked stick.

A double-sided stick has two chip-select rows which access different sets of memory devices. The two rows cannot be accessed concurrently. "Double-sided" is irrespective of the memory devices being mounted on both sides of the memory stick.

• Socket set

All of the memory sticks that are required for a single memory access or all of the memory sticks spanned by a chip-select row. A single socket set has two chip-select rows and if double-sided sticks are used these will occupy those chip-select rows.

• Bank

This term is avoided because it is unclear when needing to distinguish between chip-select rows and socket sets.

Memory Controllers

Most of the EDAC core is focused on doing Memory Controller error detection. The edac_mc_alloc(). It uses internally the struct mem_ctl_info to describe the memory controllers, with is an opaque struct for the EDAC drivers. Only the EDAC core is allowed to touch it.

enum dev_type

describe the type of memory DRAM chips used at the stick

Constants

DEV_UNKNOWN

Can't be determined, or MC doesn't support detect it

DEV_X1

1 bit for data

DEV_X2

2 bits for data

DEV_X4

4 bits for data

DEV_X8

8 bits for data

DEV_X16

16 bits for data

DEV_X32

32 bits for data

DEV_X64

64 bits for data

Description

Typical values are x4 and x8.

enum hw_event_mc_err_type

type of the detected error

Constants

HW_EVENT_ERR_CORRECTED

Corrected Error - Indicates that an ECC corrected error was detected

HW_EVENT_ERR_UNCORRECTED

Uncorrected Error - Indicates an error that can't be corrected by ECC, but it is not fatal (maybe it is on an unused memory area, or the memory controller could recover from it for example, by re-trying the operation).

HW_EVENT_ERR_DEFERRED

Deferred Error - Indicates an uncorrectable error whose handling is not urgent. This could be due to hardware data poisoning where the system can continue operation until the poisoned data is consumed. Preemptive measures may also be taken, e.g. offlining pages, etc.

HW_EVENT_ERR_FATAL

Fatal Error - Uncorrected error that could not be recovered.

HW_EVENT_ERR_INFO

Informational - The CPER spec defines a forth type of error: informational logs.

enum mem_type

memory types. For a more detailed reference, please see http://en.wikipedia.org/wiki/DRAM

Constants

MEM_EMPTY

Empty csrow

MEM_RESERVED

Reserved csrow type

MEM_UNKNOWN

Unknown csrow type

MEM_FPM

FPM - Fast Page Mode, used on systems up to 1995.

MEM_EDO

EDO - Extended data out, used on systems up to 1998.

MEM_BEDO

BEDO - Burst Extended data out, an EDO variant.

MEM_SDR

SDR - Single data rate SDRAM http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory They use 3 pins for chip select: Pins 0 and 2 are for rank 0; pins 1 and 3 are for rank 1, if the memory is dual-rank.

MEM_RDR

Registered SDR SDRAM

MEM_DDR

Double data rate SDRAM http://en.wikipedia.org/wiki/DDR_SDRAM

MEM_RDDR

Registered Double data rate SDRAM This is a variant of the DDR memories. A registered memory has a buffer inside it, hiding part of the memory details to the memory controller.

MEM_RMBS

Rambus DRAM, used on a few Pentium III/IV controllers.

MEM_DDR2

DDR2 RAM, as described at JEDEC JESD79-2F. Those memories are labeled as "PC2-" instead of "PC" to differentiate from DDR.

MEM_FB_DDR2

Fully-Buffered DDR2, as described at JEDEC Std No. 205 and JESD206. Those memories are accessed per DIMM slot, and not by a chip select signal.

MEM_RDDR2

Registered DDR2 RAM This is a variant of the DDR2 memories.

MEM_XDR

Rambus XDR It is an evolution of the original RAMBUS memories, created to compete with DDR2. Weren't used on any x86 arch, but cell_edac PPC memory controller uses it.

MEM_DDR3

DDR3 RAM

MEM_RDDR3

Registered DDR3 RAM This is a variant of the DDR3 memories.

MEM_LRDDR3

Load-Reduced DDR3 memory.

MEM_DDR4

Unbuffered DDR4 RAM

MEM_RDDR4

Registered DDR4 RAM This is a variant of the DDR4 memories.

MEM_LRDDR4

Load-Reduced DDR4 memory.

MEM_NVDIMM

Non-volatile RAM

enum edac_type

type - Error Detection and Correction capabilities and mode

Constants

EDAC_UNKNOWN

Unknown if ECC is available

EDAC_NONE

Doesn't support ECC

EDAC_RESERVED

Reserved ECC type

EDAC_PARITY

Detects parity errors

EDAC_EC

Error Checking - no correction

EDAC_SECDED

Single bit error correction, Double detection

EDAC_S2ECD2ED

Chipkill x2 devices - do these exist?

EDAC_S4ECD4ED

Chipkill x4 devices

EDAC_S8ECD8ED

Chipkill x8 devices

EDAC_S16ECD16ED

Chipkill x16 devices

enum scrub_type

scrubbing capabilities

Constants

SCRUB_UNKNOWN

Unknown if scrubber is available

SCRUB_NONE

No scrubber

SCRUB_SW_PROG

SW progressive (sequential) scrubbing

SCRUB_SW_SRC

Software scrub only errors

SCRUB_SW_PROG_SRC

Progressive software scrub from an error

SCRUB_SW_TUNABLE

Software scrub frequency is tunable

SCRUB_HW_PROG

HW progressive (sequential) scrubbing

SCRUB_HW_SRC

Hardware scrub only errors

SCRUB_HW_PROG_SRC

Progressive hardware scrub from an error

SCRUB_HW_TUNABLE

Hardware scrub frequency is tunable

enum edac_mc_layer_type

memory controller hierarchy layer

Constants

EDAC_MC_LAYER_BRANCH

memory layer is named "branch"

EDAC_MC_LAYER_CHANNEL

memory layer is named "channel"

EDAC_MC_LAYER_SLOT

memory layer is named "slot"

EDAC_MC_LAYER_CHIP_SELECT

memory layer is named "chip select"

EDAC_MC_LAYER_ALL_MEM

memory layout is unknown. All memory is mapped as a single memory area. This is used when retrieving errors from a firmware driven driver.

Description

This enum is used by the drivers to tell edac_mc_sysfs what name should be used when describing a memory stick location.

struct edac_mc_layer

describes the memory controller hierarchy

Definition

struct edac_mc_layer {
  enum edac_mc_layer_type type;
  unsigned size;
  bool is_virt_csrow;
};

Members

type

layer type

size

number of components per layer. For example, if the channel layer has two channels, size = 2

is_virt_csrow

This layer is part of the "csrow" when old API compatibility mode is enabled. Otherwise, it is a channel

struct rank_info

contains the information for one DIMM rank

Definition

struct rank_info {
  int chan_idx;
  struct csrow_info *csrow;
  struct dimm_info *dimm;
  u32 ce_count;
};

Members

chan_idx

channel number where the rank is (typically, 0 or 1)

csrow

A pointer to the chip select row structure (the parent structure). The location of the rank is given by the (csrow->csrow_idx, chan_idx) vector.

dimm

A pointer to the DIMM structure, where the DIMM label information is stored.

ce_count

number of correctable errors for this rank

Description

FIXME: Currently, the EDAC core model will assume one DIMM per rank.

This is a bad assumption, but it makes this patch easier. Later patches in this series will fix this issue.

struct edac_raw_error_desc

Raw error report structure

Definition

struct edac_raw_error_desc {
  char location[LOCATION_SIZE];
  char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
  long grain;
  u16 error_count;
  int top_layer;
  int mid_layer;
  int low_layer;
  unsigned long page_frame_number;
  unsigned long offset_in_page;
  unsigned long syndrome;
  const char *msg;
  const char *other_detail;
  bool enable_per_layer_report;
};

Members

location

location of the error

label

label of the affected DIMM(s)

grain

minimum granularity for an error report, in bytes

error_count

number of errors of the same type

top_layer

top layer of the error (layer[0])

mid_layer

middle layer of the error (layer[1])

low_layer

low layer of the error (layer[2])

page_frame_number

page where the error happened

offset_in_page

page offset

syndrome

syndrome of the error (or 0 if unknown or if the syndrome is not applicable)

msg

error message

other_detail

other driver-specific detail about the error

enable_per_layer_report

if false, the error affects all layers (typically, a memory controller error)

struct dimm_info * edac_get_dimm_by_index(struct mem_ctl_info * mci, int index)

Get DIMM info at index from a memory controller

Parameters

struct mem_ctl_info * mci

MC descriptor struct mem_ctl_info

int index

index in the memory controller's DIMM array

Description

Returns a struct dimm_info * or NULL on failure.

struct dimm_info * edac_get_dimm(struct mem_ctl_info * mci, int layer0, int layer1, int layer2)

Get DIMM info from a memory controller given by [layer0,layer1,layer2] position

Parameters

struct mem_ctl_info * mci

MC descriptor struct mem_ctl_info

int layer0

layer0 position

int layer1

layer1 position. Unused if n_layers < 2

int layer2

layer2 position. Unused if n_layers < 3

Description

For 1 layer, this function returns "dimms[layer0]";

For 2 layers, this function is similar to allocating a two-dimensional array and returning "dimms[layer0][layer1]";

For 3 layers, this function is similar to allocating a tri-dimensional array and returning "dimms[layer0][layer1][layer2]";

struct mem_ctl_info * edac_mc_alloc(unsigned int mc_num, unsigned int n_layers, struct edac_mc_layer * layers, unsigned int sz_pvt)

Allocate and partially fill a struct mem_ctl_info.

Parameters

unsigned int mc_num

Memory controller number

unsigned int n_layers

Number of MC hierarchy layers

struct edac_mc_layer * layers

Describes each layer as seen by the Memory Controller

unsigned int sz_pvt

size of private storage needed

Description

Everything is kmalloc'ed as one big chunk - more efficient. Only can be used if all structures have the same lifetime - otherwise you have to allocate and initialize your own structures.

Use edac_mc_free() to free mc structures allocated by this function.

Note

drivers handle multi-rank memories in different ways: in some drivers, one multi-rank memory stick is mapped as one entry, while, in others, a single multi-rank memory stick would be mapped into several entries. Currently, this function will allocate multiple struct dimm_info on such scenarios, as grouping the multiple ranks require drivers change.

Return

On success, return a pointer to struct mem_ctl_info pointer; NULL otherwise

const char * edac_get_owner(void)

Return the owner's mod_name of EDAC MC

Parameters

void

no arguments

Return

Pointer to mod_name string when EDAC MC is owned. NULL otherwise.

void edac_mc_free(struct mem_ctl_info * mci)

Frees a previously allocated mci structure

Parameters

struct mem_ctl_info * mci

pointer to a struct mem_ctl_info structure

bool edac_has_mcs(void)

Check if any MCs have been allocated.

Parameters

void

no arguments

Return

True if MC instances have been registered successfully. False otherwise.

struct mem_ctl_info * edac_mc_find(int idx)

Search for a mem_ctl_info structure whose index is idx.

Parameters

int idx

index to be seek

Description

If found, return a pointer to the structure. Else return NULL.

struct mem_ctl_info * find_mci_by_dev(struct device * dev)

Scan list of controllers looking for the one that manages the dev device.

Parameters

struct device * dev

pointer to a struct device related with the MCI

Return

on success, returns a pointer to struct mem_ctl_info; NULL otherwise.

struct mem_ctl_info * edac_mc_del_mc(struct device * dev)

Remove sysfs entries for mci structure associated with dev and remove mci structure from global list.

Parameters

struct device * dev

Pointer to struct device representing mci structure to remove.

Return

pointer to removed mci structure, or NULL if device not found.

int edac_mc_find_csrow_by_page(struct mem_ctl_info * mci, unsigned long page)

Ancillary routine to identify what csrow contains a memory page.

Parameters

struct mem_ctl_info * mci

pointer to a struct mem_ctl_info structure

unsigned long page

memory page to find

Return

on success, returns the csrow. -1 if not found.

void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info * mci, struct edac_raw_error_desc* e)

Reports a memory event to userspace without doing anything to discover the error location.

Parameters

const enum hw_event_mc_err_type type

severity of the error (CE/UE/Fatal)

struct mem_ctl_info * mci

a struct mem_ctl_info pointer

struct edac_raw_error_desc * e

error description

Description

This raw function is used internally by edac_mc_handle_error(). It should only be called directly when the hardware error come directly from BIOS, like in the case of APEI GHES driver.

void edac_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info * mci, const u16 error_count, const unsigned long page_frame_number, const unsigned long offset_in_page, const unsigned long syndrome, const int top_layer, const int mid_layer, const int low_layer, const char * msg, const char * other_detail)

Reports a memory event to userspace.

Parameters

const enum hw_event_mc_err_type type

severity of the error (CE/UE/Fatal)

struct mem_ctl_info * mci

a struct mem_ctl_info pointer

const u16 error_count

Number of errors of the same type

const unsigned long page_frame_number

mem page where the error occurred

const unsigned long offset_in_page

offset of the error inside the page

const unsigned long syndrome

ECC syndrome

const int top_layer

Memory layer[0] position

const int mid_layer

Memory layer[1] position

const int low_layer

Memory layer[2] position

const char * msg

Message meaningful to the end users that explains the event

const char * other_detail

Technical details about the event that may help hardware manufacturers and EDAC developers to analyse the event

PCI Controllers

The EDAC subsystem provides a mechanism to handle PCI controllers by calling the edac_pci_alloc_ctl_info(). It will use the struct edac_pci_ctl_info to describe the PCI controllers.

struct edac_pci_ctl_info * edac_pci_alloc_ctl_info(unsigned int sz_pvt, const char * edac_pci_name)

Parameters

unsigned int sz_pvt

size of the private info at struct edac_pci_ctl_info

const char * edac_pci_name

name of the PCI device

Description

The alloc() function for the 'edac_pci' control info structure.

The chip driver will allocate one of these for each edac_pci it is going to control/register with the EDAC CORE.

Return

a pointer to struct edac_pci_ctl_info on success; NULL otherwise.

void edac_pci_free_ctl_info(struct edac_pci_ctl_info * pci)

Parameters

struct edac_pci_ctl_info * pci

pointer to struct edac_pci_ctl_info

Description

Last action on the pci control structure.

Calls the remove sysfs information, which will unregister this control struct's kobj. When that kobj's ref count goes to zero, its release function will be call and then kfree() the memory.

int edac_pci_alloc_index(void)

Parameters

void

no arguments

Return

allocated index number

int edac_pci_add_device(struct edac_pci_ctl_info * pci, int edac_idx)

Parameters

struct edac_pci_ctl_info * pci

pointer to the edac_device structure to be added to the list

int edac_idx

A unique numeric identifier to be assigned to the 'edac_pci' structure.

Description

edac_pci global list and create sysfs entries associated with edac_pci structure.

Return

0 on Success, or an error code on failure

struct edac_pci_ctl_info * edac_pci_del_device(struct device * dev)

Parameters

struct device * dev

Pointer to 'struct device' representing edac_pci structure to remove

Description

Remove sysfs entries for specified edac_pci structure and then remove edac_pci structure from global list

Return

Pointer to removed edac_pci structure, or NULL if device not found

struct edac_pci_ctl_info * edac_pci_create_generic_ctl(struct device * dev, const char * mod_name)

Parameters

struct device * dev

pointer to struct device;

const char * mod_name

name of the PCI device

Description

A generic constructor for a PCI parity polling device Some systems have more than one domain of PCI busses. For systems with one domain, then this API will provide for a generic poller.

This routine calls the edac_pci_alloc_ctl_info() for the generic device, with default values

Return

Pointer to struct edac_pci_ctl_info on success, NULL on

failure.

void edac_pci_release_generic_ctl(struct edac_pci_ctl_info * pci)

Parameters

struct edac_pci_ctl_info * pci

pointer to struct edac_pci_ctl_info

Description

The release function of a generic EDAC PCI polling device

int edac_pci_create_sysfs(struct edac_pci_ctl_info * pci)

Parameters

struct edac_pci_ctl_info * pci

pointer to struct edac_pci_ctl_info

Description

Create the controls/attributes for the specified EDAC PCI device

void edac_pci_remove_sysfs(struct edac_pci_ctl_info * pci)

Parameters

struct edac_pci_ctl_info * pci

pointer to struct edac_pci_ctl_info

Description

remove the controls and attributes for this EDAC PCI device

EDAC Blocks

The EDAC subsystem also provides a generic mechanism to report errors on other parts of the hardware via edac_device_alloc_ctl_info() function.

The structures edac_dev_sysfs_block_attribute, edac_device_block, edac_device_instance and edac_device_ctl_info provide a generic or abstract 'edac_device' representation at sysfs.

This set of structures and the code that implements the APIs for the same, provide for registering EDAC type devices which are NOT standard memory or PCI, like:

• CPU caches (L1 and L2)
• DMA engines
• Core CPU switches
• Fabric switch units
• PCIe interface controllers
• other EDAC/ECC type devices that can be monitored for errors, etc.

It allows for a 2 level set of hierarchy.

For example, a cache could be composed of L1, L2 and L3 levels of cache. Each CPU core would have its own L1 cache, while sharing L2 and maybe L3 caches. On such case, those can be represented via the following sysfs nodes:

/sys/devices/system/edac/..

pci/            <existing pci directory (if available)>
mc/             <existing memory device directory>
cpu/cpu0/..     <L1 and L2 block directory>
        /L1-cache/ce_count
                 /ue_count
        /L2-cache/ce_count
                 /ue_count
cpu/cpu1/..     <L1 and L2 block directory>
        /L1-cache/ce_count
                 /ue_count
        /L2-cache/ce_count
                 /ue_count
...

the L1 and L2 directories would be "edac_device_block's"

int edac_device_add_device(struct edac_device_ctl_info * edac_dev)

Parameters

struct edac_device_ctl_info * edac_dev

pointer to edac_device structure to be added to the list 'edac_device' structure.

Description

edac_device global list and create sysfs entries associated with edac_device structure.

Return

0 on Success, or an error code on failure

struct edac_device_ctl_info * edac_device_del_device(struct device * dev)

Parameters

struct device * dev

Pointer to struct device representing the edac device structure to remove.

Description

Remove sysfs entries for specified edac_device structure and then remove edac_device structure from global list

Return

Pointer to removed edac_device structure, or NULL if device not found.

void edac_device_handle_ce_count(struct edac_device_ctl_info * edac_dev, unsigned int count, int inst_nr, int block_nr, const char * msg)

Parameters

struct edac_device_ctl_info * edac_dev

pointer to struct edac_device_ctl_info

unsigned int count

Number of errors to log.

int inst_nr

number of the instance where the CE error happened

int block_nr

number of the block where the CE error happened

const char * msg

message to be printed

void edac_device_handle_ue_count(struct edac_device_ctl_info * edac_dev, unsigned int count, int inst_nr, int block_nr, const char * msg)

Parameters

struct edac_device_ctl_info * edac_dev

pointer to struct edac_device_ctl_info

unsigned int count

Number of errors to log.

int inst_nr

number of the instance where the CE error happened

int block_nr

number of the block where the CE error happened

const char * msg

message to be printed

void edac_device_handle_ce(struct edac_device_ctl_info * edac_dev, int inst_nr, int block_nr, const char * msg)

Parameters

struct edac_device_ctl_info * edac_dev

pointer to struct edac_device_ctl_info

int inst_nr

number of the instance where the CE error happened

int block_nr

number of the block where the CE error happened

const char * msg

message to be printed

void edac_device_handle_ue(struct edac_device_ctl_info * edac_dev, int inst_nr, int block_nr, const char * msg)

Parameters

struct edac_device_ctl_info * edac_dev

pointer to struct edac_device_ctl_info

int inst_nr

number of the instance where the UE error happened

int block_nr

number of the block where the UE error happened

const char * msg

message to be printed

int edac_device_alloc_index(void)

Parameters

void

no arguments

Return

allocated index number

2. How to use it

EDAC is maintained and written by:

 Doug Thompson, Dave Jiang, Dave Peterson et al,
original author: Thayne Harbaugh,

Contact:
website: bluesmoke.sourceforge.net
mailing list: bluesmoke-devel@lists.sourceforge.net

"bluesmoke" was the name for this device driver when it was "out-of-tree"
and maintained at sourceforge.net.  When it was pushed into 2.6.16 for the
first time, it was renamed to 'EDAC'.

The bluesmoke project at sourceforge.net is now utilized as a 'staging area'
for EDAC development, before it is sent upstream to kernel.org

At the bluesmoke/EDAC project site is a series of quilt patches against
recent kernels, stored in a SVN repository. For easier downloading, there
is also a tarball snapshot available.

============================================================================
EDAC PURPOSE

The 'edac' kernel module goal is to detect and report errors that occur
within the computer system running under linux.

MEMORY

In the initial release, memory Correctable Errors (CE) and Uncorrectable
Errors (UE) are the primary errors being harvested. These types of errors
are harvested by the 'edac_mc' class of device.

Detecting CE events, then harvesting those events and reporting them,
CAN be a predictor of future UE events.  With CE events, the system can
continue to operate, but with less safety. Preventive maintenance and
proactive part replacement of memory DIMMs exhibiting CEs can reduce
the likelihood of the dreaded UE events and system 'panics'.

NON-MEMORY

A new feature for EDAC, the edac_device class of device, was added in
the 2.6.23 version of the kernel.

This new device type allows for non-memory type of ECC hardware detectors
to have their states harvested and presented to userspace via the sysfs
interface.

Some architectures have ECC detectors for L1, L2 and L3 caches, along with DMA
engines, fabric switches, main data path switches, interconnections,
and various other hardware data paths. If the hardware reports it, then
a edac_device device probably can be constructed to harvest and present
that to userspace.

PCI BUS SCANNING

In addition, PCI Bus Parity and SERR Errors are scanned for on PCI devices
in order to determine if errors are occurring on data transfers.

The presence of PCI Parity errors must be examined with a grain of salt.
There are several add-in adapters that do NOT follow the PCI specification
with regards to Parity generation and reporting. The specification says
the vendor should tie the parity status bits to 0 if they do not intend
to generate parity.  Some vendors do not do this, and thus the parity bit
can "float" giving false positives.

In the kernel there is a PCI device attribute located in sysfs that is
checked by the EDAC PCI scanning code. If that attribute is set,
PCI parity/error scanning is skipped for that device. The attribute
is:

 broken_parity_status

as is located in /sys/devices/pci<XXX>/0000:XX:YY.Z directories for
PCI devices.

FUTURE HARDWARE SCANNING

EDAC will have future error detectors that will be integrated with
EDAC or added to it, in the following list:

 MCE Machine Check Exception
MCA Machine Check Architecture
NMI NMI notification of ECC errors
MSRs  Machine Specific Register error cases
and other mechanisms.

These errors are usually bus errors, ECC errors, thermal throttling
and the like.

============================================================================
EDAC VERSIONING

EDAC is composed of a "core" module (edac_core.ko) and several Memory
Controller (MC) driver modules. On a given system, the CORE
is loaded and one MC driver will be loaded. Both the CORE and
the MC driver (or edac_device driver) have individual versions that reflect
current release level of their respective modules.

Thus, to "report" on what version a system is running, one must report both
the CORE's and the MC driver's versions.

LOADING

If 'edac' was statically linked with the kernel then no loading is
necessary.  If 'edac' was built as modules then simply modprobe the
'edac' pieces that you need.  You should be able to modprobe
hardware-specific modules and have the dependencies load the necessary core
modules.

Example:

$> modprobe amd76x_edac

loads both the amd76x_edac.ko memory controller module and the edac_mc.ko
core module.

============================================================================
EDAC sysfs INTERFACE

EDAC presents a 'sysfs' interface for control, reporting and attribute
reporting purposes.

EDAC lives in the /sys/devices/system/edac directory.

Within this directory there currently reside 2 'edac' components:

 mc memory controller(s) system
pci PCI control and status system

============================================================================
Memory Controller (mc) Model

First a background on the memory controller's model abstracted in EDAC.
Each 'mc' device controls a set of DIMM memory modules. These modules are
laid out in a Chip-Select Row (csrowX) and Channel table (chX). There can
be multiple csrows and multiple channels.

Memory controllers allow for several csrows, with 8 csrows being a typical value.
Yet, the actual number of csrows depends on the electrical "loading"
of a given motherboard, memory controller and DIMM characteristics.

Dual channels allows for 128 bit data transfers to the CPU from memory.
Some newer chipsets allow for more than 2 channels, like Fully Buffered DIMMs
(FB-DIMMs). The following example will assume 2 channels:

  Channel 0 Channel 1
===================================
csrow0 | DIMM_A0 | DIMM_B0 |
csrow1 | DIMM_A0 | DIMM_B0 |
===================================

 ===================================
csrow2 | DIMM_A1 | DIMM_B1 |
csrow3 | DIMM_A1 | DIMM_B1 |
===================================

In the above example table there are 4 physical slots on the motherboard
for memory DIMMs:

 DIMM_A0
DIMM_B0
DIMM_A1
DIMM_B1

Labels for these slots are usually silk screened on the motherboard. Slots
labeled 'A' are channel 0 in this example. Slots labeled 'B'
are channel 1. Notice that there are two csrows possible on a
physical DIMM. These csrows are allocated their csrow assignment
based on the slot into which the memory DIMM is placed. Thus, when 1 DIMM
is placed in each Channel, the csrows cross both DIMMs.

Memory DIMMs come single or dual "ranked". A rank is a populated csrow.
Thus, 2 single ranked DIMMs, placed in slots DIMM_A0 and DIMM_B0 above
will have 1 csrow, csrow0. csrow1 will be empty. On the other hand,
when 2 dual ranked DIMMs are similarly placed, then both csrow0 and
csrow1 will be populated. The pattern repeats itself for csrow2 and
csrow3.

The representation of the above is reflected in the directory tree
in EDAC's sysfs interface. Starting in directory
/sys/devices/system/edac/mc each memory controller will be represented
by its own 'mcX' directory, where 'X' is the index of the MC.

 ..../edac/mc/
     |
     |->mc0
     |->mc1
     |->mc2
     ....

Under each 'mcX' directory each 'csrowX' is again represented by a
'csrowX', where 'X' is the csrow index:

 .../mc/mc0/
  |
  |->csrow0
  |->csrow2
  |->csrow3
  ....

Notice that there is no csrow1, which indicates that csrow0 is
composed of a single ranked DIMMs. This should also apply in both
Channels, in order to have dual-channel mode be operational. Since
both csrow2 and csrow3 are populated, this indicates a dual ranked
set of DIMMs for channels 0 and 1.

Within each of the 'mcX' and 'csrowX' directories are several
EDAC control and attribute files.

============================================================================
'mcX' DIRECTORIES

In 'mcX' directories are EDAC control and attribute files for
this 'X' instance of the memory controllers.

For a description of the sysfs API, please see:
Documentation/ABI/testing/sysfs/devices-edac

============================================================================
'csrowX' DIRECTORIES

When CONFIG_EDAC_LEGACY_SYSFS is enabled, the sysfs will contain the
csrowX directories. As this API doesn't work properly for Rambus, FB-DIMMs
and modern Intel Memory Controllers, this is being deprecated in favor
of dimmX directories.

In the 'csrowX' directories are EDAC control and attribute files for
this 'X' instance of csrow:

Total Uncorrectable Errors count attribute file:

 'ue_count'

 This attribute file displays the total count of uncorrectable
errors that have occurred on this csrow. If panic_on_ue is set
this counter will not have a chance to increment, since EDAC
will panic the system.

Total Correctable Errors count attribute file:

 'ce_count'

 This attribute file displays the total count of correctable
errors that have occurred on this csrow. This
count is very important to examine. CEs provide early
indications that a DIMM is beginning to fail. This count
field should be monitored for non-zero values and report
such information to the system administrator.

Total memory managed by this csrow attribute file:

 'size_mb'

 This attribute file displays, in count of megabytes, of memory
that this csrow contains.

Memory Type attribute file:

 'mem_type'

 This attribute file will display what type of memory is currently
on this csrow. Normally, either buffered or unbuffered memory.
Examples:
  Registered-DDR
  Unbuffered-DDR

EDAC Mode of operation attribute file:

 'edac_mode'

 This attribute file will display what type of Error detection
and correction is being utilized.

Device type attribute file:

 'dev_type'

 This attribute file will display what type of DRAM device is
being utilized on this DIMM.
Examples:
  x1
  x2
  x4
  x8

Channel 0 CE Count attribute file:

 'ch0_ce_count'

 This attribute file will display the count of CEs on this
DIMM located in channel 0.

Channel 0 UE Count attribute file:

 'ch0_ue_count'

 This attribute file will display the count of UEs on this
DIMM located in channel 0.

Channel 0 DIMM Label control file:

 'ch0_dimm_label'

 This control file allows this DIMM to have a label assigned
to it. With this label in the module, when errors occur
the output can provide the DIMM label in the system log.
This becomes vital for panic events to isolate the
cause of the UE event.

 DIMM Labels must be assigned after booting, with information
that correctly identifies the physical slot with its
silk screen label. This information is currently very
motherboard specific and determination of this information
must occur in userland at this time.

Channel 1 CE Count attribute file:

 'ch1_ce_count'

 This attribute file will display the count of CEs on this
DIMM located in channel 1.

Channel 1 UE Count attribute file:

 'ch1_ue_count'

 This attribute file will display the count of UEs on this
DIMM located in channel 0.

Channel 1 DIMM Label control file:

 'ch1_dimm_label'

 This control file allows this DIMM to have a label assigned
to it. With this label in the module, when errors occur
the output can provide the DIMM label in the system log.
This becomes vital for panic events to isolate the
cause of the UE event.

 DIMM Labels must be assigned after booting, with information
that correctly identifies the physical slot with its
silk screen label. This information is currently very
motherboard specific and determination of this information
must occur in userland at this time.

============================================================================
SYSTEM LOGGING

If logging for UEs and CEs are enabled then system logs will have
error notices indicating errors that have been detected:

EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0,
channel 1 "DIMM_B1": amd76x_edac

EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0,
channel 1 "DIMM_B1": amd76x_edac

The structure of the message is:
the memory controller   (MC0)
Error type    (CE)
memory page    (0x283)
offset in the page   (0xce0)
the byte granularity    (grain 8)
  or resolution of the error
the error syndrome   (0xb741)
memory row    (row 0)
memory channel    (channel 1)
DIMM label, if set prior  (DIMM B1
and then an optional, driver-specific message that may
  have additional information.

Both UEs and CEs with no info will lack all but memory controller,
error type, a notice of "no info" and then an optional,
driver-specific error message.

============================================================================
PCI Bus Parity Detection

On Header Type 00 devices the primary status is looked at
for any parity error regardless of whether Parity is enabled on the
device.  (The spec indicates parity is generated in some cases).
On Header Type 01 bridges, the secondary status register is also
looked at to see if parity occurred on the bus on the other side of
the bridge.

SYSFS CONFIGURATION

Under /sys/devices/system/edac/pci are control and attribute files as follows:

Enable/Disable PCI Parity checking control file:

 'check_pci_parity'

 This control file enables or disables the PCI Bus Parity scanning
operation. Writing a 1 to this file enables the scanning. Writing
a 0 to this file disables the scanning.

 Enable:
echo "1" >/sys/devices/system/edac/pci/check_pci_parity

 Disable:
echo "0" >/sys/devices/system/edac/pci/check_pci_parity

Parity Count:

 'pci_parity_count'

 This attribute file will display the number of parity errors that
have been detected.

============================================================================
MODULE PARAMETERS

Panic on UE control file:

 'edac_mc_panic_on_ue'

 An uncorrectable error will cause a machine panic.  This is usually
desirable.  It is a bad idea to continue when an uncorrectable error
occurs - it is indeterminate what was uncorrected and the operating
system context might be so mangled that continuing will lead to further
corruption. If the kernel has MCE configured, then EDAC will never
notice the UE.

 LOAD TIME: module/kernel parameter: edac_mc_panic_on_ue=[0|1]

 RUN TIME:  echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue

Log UE control file:

 'edac_mc_log_ue'

 Generate kernel messages describing uncorrectable errors.  These errors
are reported through the system message log system.  UE statistics
will be accumulated even when UE logging is disabled.

 LOAD TIME: module/kernel parameter: edac_mc_log_ue=[0|1]

 RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue

Log CE control file:

 'edac_mc_log_ce'

 Generate kernel messages describing correctable errors.  These
errors are reported through the system message log system.
CE statistics will be accumulated even when CE logging is disabled.

 LOAD TIME: module/kernel parameter: edac_mc_log_ce=[0|1]

 RUN TIME: echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce

Polling period control file:

 'edac_mc_poll_msec'

 The time period, in milliseconds, for polling for error information.
Too small a value wastes resources.  Too large a value might delay
necessary handling of errors and might loose valuable information for
locating the error.  1000 milliseconds (once each second) is the current
default. Systems which require all the bandwidth they can get, may
increase this.

 LOAD TIME: module/kernel parameter: edac_mc_poll_msec=[0|1]

 RUN TIME: echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec

Panic on PCI PARITY Error:

 'panic_on_pci_parity'

 This control files enables or disables panicking when a parity
error has been detected.

 module/kernel parameter: edac_panic_on_pci_pe=[0|1]

 Enable:
echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe

 Disable:
echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe

=======================================================================

EDAC_DEVICE type of device

In the header file, edac_core.h, there is a series of edac_device structures
and APIs for the EDAC_DEVICE.

User space access to an edac_device is through the sysfs interface.

At the location /sys/devices/system/edac (sysfs) new edac_device devices will
appear.

There is a three level tree beneath the above 'edac' directory. For example,
the 'test_device_edac' device (found at the bluesmoke.sourceforget.net website)
installs itself as:

 /sys/devices/systm/edac/test-instance

in this directory are various controls, a symlink and one or more 'instance'
directories.

The standard default controls are:

 log_ce  boolean to log CE events
log_ue  boolean to log UE events
panic_on_ue boolean to 'panic' the system if an UE is encountered
   (default off, can be set true via startup script)
poll_msec time period between POLL cycles for events

The test_device_edac device adds at least one of its own custom control:

 test_bits which in the current test driver does nothing but
   show how it is installed. A ported driver can
   add one or more such controls and/or attributes
   for specific uses.
   One out-of-tree driver uses controls here to allow
   for ERROR INJECTION operations to hardware
   injection registers

The symlink points to the 'struct dev' that is registered for this edac_device.

INSTANCES

One or more instance directories are present. For the 'test_device_edac' case:

 test-instance0

In this directory there are two default counter attributes, which are totals of
counter in deeper subdirectories.

 ce_count total of CE events of subdirectories
ue_count total of UE events of subdirectories

BLOCKS

At the lowest directory level is the 'block' directory. There can be 0, 1
or more blocks specified in each instance.

 test-block0

In this directory the default attributes are:

 ce_count which is counter of CE events for this 'block'
   of hardware being monitored
ue_count which is counter of UE events for this 'block'
   of hardware being monitored

The 'test_device_edac' device adds 4 attributes and 1 control:

 test-block-bits-0 for every POLL cycle this counter
    is incremented
test-block-bits-1 every 10 cycles, this counter is bumped once,
    and test-block-bits-0 is set to 0
test-block-bits-2 every 100 cycles, this counter is bumped once,
    and test-block-bits-1 is set to 0
test-block-bits-3 every 1000 cycles, this counter is bumped once,
    and test-block-bits-2 is set to 0

 reset-counters  writing ANY thing to this control will
    reset all the above counters.

Use of the 'test_device_edac' driver should any others to create their own
unique drivers for their hardware systems.

The 'test_device_edac' sample driver is located at the
bluesmoke.sourceforge.net project site for EDAC.

=======================================================================
NEHALEM USAGE OF EDAC APIs

This chapter documents some EXPERIMENTAL mappings for EDAC API to handle
Nehalem EDAC driver. They will likely be changed on future versions
of the driver.

Due to the way Nehalem exports Memory Controller data, some adjustments
were done at i7core_edac driver. This chapter will cover those differences

1) On Nehalem, there are one Memory Controller per Quick Patch Interconnect
   (QPI). At the driver, the term "socket" means one QPI. This is
   associated with a physical CPU socket.

   Each MC have 3 physical read channels, 3 physical write channels and
   3 logic channels. The driver currently sees it as just 3 channels.
   Each channel can have up to 3 DIMMs.

   The minimum known unity is DIMMs. There are no information about csrows.
   As EDAC API maps the minimum unity is csrows, the driver sequencially
   maps channel/dimm into different csrows.

   For example, supposing the following layout:
Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs
   dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
   dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400
        Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs
   dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs
   dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
   The driver will map it as:
csrow0: channel 0, dimm0
csrow1: channel 0, dimm1
csrow2: channel 1, dimm0
csrow3: channel 2, dimm0

exports one
   DIMM per csrow.

   Each QPI is exported as a different memory controller.

2) Nehalem MC has the hability to generate errors. The driver implements this
   functionality via some error injection nodes:

   For injecting a memory error, there are some sysfs nodes, under
   /sys/devices/system/edac/mc/mc?/:

   inject_addrmatch/*:
      Controls the error injection mask register. It is possible to specify
      several characteristics of the address to match an error code:
         dimm = the affected dimm. Numbers are relative to a channel;
         rank = the memory rank;
         channel = the channel that will generate an error;
         bank = the affected bank;
         page = the page address;
         column (or col) = the address column.
      each of the above values can be set to "any" to match any valid value.

      At driver init, all values are set to any.

      For example, to generate an error at rank 1 of dimm 2, for any channel,
      any bank, any page, any column:
  echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
  echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank

 To return to the default behaviour of matching any, you can do:
  echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
  echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank

   inject_eccmask:
       specifies what bits will have troubles,

   inject_section:
       specifies what ECC cache section will get the error:
  3 for both
  2 for the highest
  1 for the lowest

   inject_type:
       specifies the type of error, being a combination of the following bits:
  bit 0 - repeat
  bit 1 - ecc
  bit 2 - parity

       inject_enable starts the error generation when something different
       than 0 is written.

   All inject vars can be read. root permission is needed for write.

   Datasheet states that the error will only be generated after a write on an
   address that matches inject_addrmatch. It seems, however, that reading will
   also produce an error.

   For example, the following code will generate an error for any write access
   at socket 0, on any DIMM/address on channel 2:

   echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel
   echo 2 >/sys/devices/system/edac/mc/mc0/inject_type
   echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask
   echo 3 >/sys/devices/system/edac/mc/mc0/inject_section
   echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable
   dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null

   For socket 1, it is needed to replace "mc0" by "mc1" at the above
   commands.

   The generated error message will look like:

   EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))

3) Nehalem specific Corrected Error memory counters

   Nehalem have some registers to count memory errors. The driver uses those
   registers to report Corrected Errors on devices with Registered Dimms.

   However, those counters don't work with Unregistered Dimms. As the chipset
   offers some counters that also work with UDIMMS (but with a worse level of
   granularity than the default ones), the driver exposes those registers for
   UDIMM memories.

   They can be read by looking at the contents of all_channel_counts/

   $ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0
0
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1
0
/sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2
0

   What happens here is that errors on different csrows, but at the same
   dimm number will increment the same counter.
   So, in this memory mapping:
csrow0: channel 0, dimm0
csrow1: channel 0, dimm1
csrow2: channel 1, dimm0
csrow3: channel 2, dimm0
   The hardware will increment udimm0 for an error at the first dimm at either
csrow0, csrow2  or csrow3;
   The hardware will increment udimm1 for an error at the second dimm at either
csrow0, csrow2  or csrow3;
   The hardware will increment udimm2 for an error at the third dimm at either
csrow0, csrow2  or csrow3;

4) Standard error counters

   The standard error counters are generated when an mcelog error is received
   by the driver. Since, with udimm, this is counted by software, it is
   possible that some errors could be lost. With rdimm's, they displays the
   contents of the registers