一、版本说明

- Python版本: Python 3.12.3
- ninja版本 : ninja version 1.11.1
- CMake版本 : cmake version 3.28.3
- 芯片型号  : ESP32-S3
- IDF版本   : ESP-IDF v5.4.1-dirty

---

二、例程步骤

/* 配置定时器 */
1. esp_err_t ledc_timer_config(const ledc_timer_config_t *timer_conf)

/* 配置通道 */
2. esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)

/* 设置占空比 */
3. esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty)

/* 更新占空比 */
4. esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel)

---

三、例程源码

#include "Ledc.h"

#include "driver/ledc.h"

#define LEDC_SPEED_MODE     (LEDC_LOW_SPEED_MODE)
#define LEDC_TIMER_NUM      (LEDC_TIMER_0)
#define LEDC_RESOLUTION     (LEDC_TIMER_10_BIT)
#define LEDC_FREQ_HZ        (10000)
#define LEDC_CHANNEL        (LEDC_CHANNEL_2)
#define LEDC_GPIO_NUM       (GPIO_NUM_10)


void ledc_init(void)
{
    ledc_timer_config_t ledc_timer = 
    {
        .speed_mode       = LEDC_SPEED_MODE, //timer mode
        .timer_num        = LEDC_TIMER_NUM,  //timer index
        .duty_resolution  = LEDC_RESOLUTION, //resolution of PWM duty
        .freq_hz          = LEDC_FREQ_HZ,    //PWM frequency
        .clk_cfg          = LEDC_AUTO_CLK,   //automatic clock source selection
    };
    ledc_timer_config(&ledc_timer);

    ledc_channel_config_t ledc_channel = 
    {
        .channel    = LEDC_CHANNEL,      //channel number
        .timer_sel  = LEDC_TIMER_NUM,    //timer index
        .intr_type  = LEDC_INTR_DISABLE, //interrupt type
        .speed_mode = LEDC_SPEED_MODE,   //timer mode
        .gpio_num   = LEDC_GPIO_NUM,     //output IO
        .duty       = 0,                 //set duty
        .hpoint     = 0,                 //set hpoint
    };
    ledc_channel_config(&ledc_channel);


    uint32_t duty_25_percent = (1 << (LEDC_RESOLUTION & 0xFF)) / 4;
    ESP_ERROR_CHECK(ledc_set_duty(LEDC_SPEED_MODE, LEDC_CHANNEL, duty_25_percent));
    ESP_ERROR_CHECK(ledc_update_duty(LEDC_SPEED_MODE, LEDC_CHANNEL));
}

---

四、主函数

#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "nvs_flash.h"
#include "esp_system.h"
#include "esp_chip_info.h"
#include "esp_psram.h"
#include "esp_flash.h"
#include "driver/gpio.h"

#include "sys_clock.h"
#include "Ledc.h"


void app_main(void)
{
    esp_err_t ret;
    uint32_t flash_size;
    esp_chip_info_t chip_info; 

    ret = nvs_flash_init();
    if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND)
    {
        ESP_ERROR_CHECK(nvs_flash_erase());
        ret = nvs_flash_init();
    }
    esp_flash_get_size(NULL, &flash_size);
    esp_chip_info(&chip_info);
    printf("内核CPU数量%d\n",chip_info.cores); 
    printf("FLASH Size:%ld MB Flash\r\n",flash_size / (1024 * 1024));
    printf("PSRAM Size:%d Bytes\r\n", esp_psram_get_size());

    ledc_init();

    while(1)
    {
        vTaskDelay(5000);
    }
}

---

五、CMakeList文件

# CMake最低版本
cmake_minimum_required(VERSION 3.16)

# 指定额外组件搜索目录
set(EXTRA_COMPONENT_DIRS components/Middlewares)

# 强制编译器彩色显示编译信息
add_compile_options(-fdiagnostics-color=always)

# 指定编译目标芯片
set(IDF_TARGET esp32s3)

# 日志输出命令
message(STATUS "Current IDF_PATH from environment: $ENV{IDF_PATH}")

# ESP-IDF核心构建脚本启动ESP-IDF构建系统
include($ENV{IDF_PATH}/tools/cmake/project.cmake)

# 定义工程名称
project(main)

idf_component_register(SRCS "main.c"
                    INCLUDE_DIRS ".")

set(src_dirs 
            Clock
            PWM)

set(include_dirs 
                Clock
                PWM)

set(requires    driver 
                nvs_flash 
                esp_psram 
                spi_flash)

# idf_component_register(SRC_DIRS ${src_dirs} INCLUDE_DIRS ${include_dirs} REQUIRES ${requires})
idf_component_register(SRC_DIRS ${src_dirs}
                       INCLUDE_DIRS ${include_dirs}
                       REQUIRES ${requires})
component_compile_options(-ffast-math -O3 -Wno-error=format -Wno-format)

---

六、运行结果

--- esp-idf-monitor 1.6.2 on /dev/ttyACM0 115200
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x28 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce2820,len:0x170c
load:0x403c8700,len:0x4
load:0x403c8704,len:0xec4
load:0x403cb700,len:0x318c
entry 0x403c8950
I (27) boot: ESP-IDF v5.4.1-dirty 2nd stage bootloader
I (27) boot: compile time Feb 10 2026 10:37:28
I (27) boot: Multicore bootloader
I (28) boot: chip revision: v0.2
I (30) boot: efuse block revision: v1.3
I (34) qio_mode: Enabling default flash chip QIO
I (38) boot.esp32s3: Boot SPI Speed : 80MHz
I (42) boot.esp32s3: SPI Mode       : QIO
I (46) boot.esp32s3: SPI Flash Size : 16MB
I (50) boot: Enabling RNG early entropy source...
I (54) boot: Partition Table:
I (57) boot: ## Label            Usage          Type ST Offset   Length
I (63) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (70) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (76) boot:  2 factory          factory app      00 00 00010000 001f0000
I (83) boot:  3 vfs              Unknown data     01 81 00200000 00a00000
I (89) boot:  4 storage          Unknown data     01 82 00c00000 00400000
I (96) boot: End of partition table
I (99) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=0b0d0h ( 45264) map
I (113) esp_image: segment 1: paddr=0001b0f8 vaddr=3fc94000 size=02f4ch ( 12108) load
I (116) esp_image: segment 2: paddr=0001e04c vaddr=40374000 size=01fcch (  8140) load
I (123) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=1bec4h (114372) map
I (146) esp_image: segment 4: paddr=0003beec vaddr=40375fcc size=0dfc8h ( 57288) load
I (157) esp_image: segment 5: paddr=00049ebc vaddr=600fe100 size=0001ch (    28) load
I (164) boot: Loaded app from partition at offset 0x10000
I (164) boot: Disabling RNG early entropy source...
I (175) octal_psram: vendor id    : 0x0d (AP)
I (175) octal_psram: dev id       : 0x02 (generation 3)
I (175) octal_psram: density      : 0x03 (64 Mbit)
I (177) octal_psram: good-die     : 0x01 (Pass)
I (181) octal_psram: Latency      : 0x01 (Fixed)
I (186) octal_psram: VCC          : 0x01 (3V)
I (190) octal_psram: SRF          : 0x01 (Fast Refresh)
I (195) octal_psram: BurstType    : 0x01 (Hybrid Wrap)
I (200) octal_psram: BurstLen     : 0x01 (32 Byte)
I (204) octal_psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (209) octal_psram: DriveStrength: 0x00 (1/1)
I (214) MSPI Timing: PSRAM timing tuning index: 4
I (218) esp_psram: Found 8MB PSRAM device
I (222) esp_psram: Speed: 80MHz
I (225) cpu_start: Multicore app
I (654) esp_psram: SPI SRAM memory test OK
I (662) cpu_start: Pro cpu start user code
I (662) cpu_start: cpu freq: 240000000 Hz
I (662) app_init: Application information:
I (662) app_init: Project name:     main
I (666) app_init: App version:      1
I (669) app_init: Compile time:     Feb 10 2026 10:36:49
I (674) app_init: ELF file SHA256:  d17d661c0...
I (679) app_init: ESP-IDF:          v5.4.1-dirty
I (683) efuse_init: Min chip rev:     v0.0
I (687) efuse_init: Max chip rev:     v0.99 
I (691) efuse_init: Chip rev:         v0.2
I (695) heap_init: Initializing. RAM available for dynamic allocation:
I (701) heap_init: At 3FC978E0 len 00051E30 (327 KiB): RAM
I (706) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
I (711) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (717) heap_init: At 600FE11C len 00001ECC (7 KiB): RTCRAM
I (722) esp_psram: Adding pool of 8192K of PSRAM memory to heap allocator
I (729) spi_flash: detected chip: generic
I (732) spi_flash: flash io: qio
I (735) sleep_gpio: Configure to isolate all GPIO pins in sleep state
I (741) sleep_gpio: Enable automatic switching of GPIO sleep configuration
I (748) main_task: Started on CPU0
I (772) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations
I (772) main_task: Calling app_main()
内核CPU数量2
FLASH Size:16 MB Flash
PSRAM Size:8388608 Bytes